The present invention relates to a semiconductor memory device, and more particularly relates to a flash memory device and a method of inputting data.
A common flash memory device can be erased and reprogrammed many times and has the ability to retain data even when power is turned off, and so it has been employed in various semiconductor memory devices.
The flash memory device employs page buffers for speeding up the programming or reading of large data. Accordingly, program and read operations in the flash memory device are performed on a page basis by the page buffers.
FIG. 1 is a view illustrating circuitry of a Y-decoder section in a common flash memory device.
Referring to FIG. 1, the Y-decoder section 10 is employed to input data into one of the page buffers PB0 to PBn. FIG. 1 shows schematically latch LAT0 and a data input circuit DIC0 of page buffer PB0, in the left top corner. The Y-decoder section 10 includes a plurality of selecting sections 10A to 10S connected between the page buffers PB0 to PBn and data lines DL0 to DLk.
The selecting sections 10A to 10S have the same structure, e.g. 10A includes N-MOS transistors NC0 to NCc, NB0 to NBb, NA0 to NAx.
The Y-decoder section 10 connects a page buffer selected from the page buffers PB0 to PBn to a data line, e.g. DL0 selected from the data lines DL0 to DLk in response to Y-decoder driving signals YC_DRV<0:C>, YB_DRV<0:B> and YA_DRV<0:A>, thereby forming a data input path.
An operating controller 11 is connected respectively to the data lines DL0 to DLk, thereby supplying the data lines DL0 to DLk with a ground voltage or a supply voltage in accordance with discharging signals DL0_DIS to DLk_DIS. Accordingly, the data input path is discharged to a low level by the discharging signals DL0_DIS to DLk_DIS in a process of inputting data.
FIG. 2 is a timing diagram illustrating signals related to operation of inputting data using the Y-decoder section in FIG. 1.
Hereinafter, a process of inputting data in the flash memory device will be described in detail with reference to FIG. 1 and FIG. 2. It is assumed that first data “0” is inputted into page buffers PB0 to PB3, and second data “1” is inputted into page buffers PBk to PBk+3.
The operating controller 11 connects data line, e.g. DL0 to the supply voltage in response to a discharge signal having low level. Additionally, the Y-decoder section 10 connects internal data lines YA, YB and YC to the data line DL0 in accordance with first, second and third driving signals YC_DRV<0:C>, YB_DRV<0:B> and YA_DRV<0:A> having high level. As a result, the internal data lines YA, YB and YC are precharged to high level.
Then, the first, second and third driving signals YC_DRV<0:C>, YB_DRV<0:B> and YA_DRV<0:A> are disabled so that the data line DL0 is disconnected from the internal data lines YA, YB and YC
Subsequently, the operating controller 11 connects the data line, e.g. DL0 to the ground voltage in response to discharge signal DL0_DIS having high level, thereby discharging the data line DL0. The N-MOS transistor NC0 and the N-MOS transistor NB0 are turned on in response to the third driving signal YC_DRV<0> and the second driving signal YB_DRV<0>, respectively, and so the first internal data line YC is connected to the data line DL0, and the second internal data line YB is connected to the first internal data line YC. As a result, the data line DL0 is connected to the second internal data line YB through the first internal data line YC.
Then, the N-MOS transistor NA0 is turned on in response to the first driving signal YA_DRV<0>, and so the input/output data line YA is connected to the second internal data line YB. In this case, an N-MOS transistor NDI1 in the data input circuit DIC0 is turned on in response to a data input signal nDI, and so the input/output data line YA is connected to the latch LAT0. Accordingly, the data line DL0 coupled to the ground voltage is connected to the first internal data line YC, the second internal data line YB, the input/output data line YA and the latch LAT0 in the page buffer PB0, and so “0” data is inputted into the page buffer PB0.
Subsequently, first driving signals YA_DRV<1> to YA_DRV<3> are enabled in sequence, and so first data “0” is inputted in sequence into the page buffer PB1 to PB3. The operating controller 11 connects the data line DL0 to the supply voltage in response to the discharge signal DL0_DIS having low level. In addition, the Y-decoder section 10 connects the internal data lines YB and YC and the input/output data line YA to the data line DL0 in accordance with the first, second and third driving signals YC_DRV<0:C>, YB_DRV<0:B> and YA_DRV<0:A> having high level. Consequently, the input/output data line YA and the internal data lines YB and YC are precharged to a high level. Here, since many internal data lines must be precharged through one data line, e.g. DL0 during a predetermined period of time, the internal data lines may be precharged incompletely.
Then, the second data “1” is inputted into the page buffers PBk to PBk+3. Particularly, the third driving signal YC_DRV<0> is disabled, and the third driving signal YC_DRV<C> is enabled. Accordingly, new data path {circle around (2)} different from the data path {circle around (1)} formed when the first data was inputted is formed, and so the second data is inputted into the selected page buffers PBk to PBk+3. In this case, the first data “0” may be with loading condition by the data lines precharged incompletely in the precharging process, e.g. input/output data line YA connected to the page buffers PB0 to PB3.
This phenomenon occurs because the data lines are increased as the data capacity of a memory device is increased, and the memory device uses lower voltages, and so data lines are precharged incompletely.
In this case, the second data “1” is inputted into the page buffers PBk to PBk+3 accordingly as the data input signal DI is provided. In case that the input/output data line YA connected to the page buffers PB0 to PB3 is precharged incompletely, i.e. keeps low level, the second data “1” is inputted again into the page buffers PB0 to PB3 which were latching the first data “0” as shown in ‘A’ of FIG. 2, and so errors may occur in the process of inputting the data.